IBM continues to develop a strategy to reduce the size of transistors. It is expected that in 2019 their length will be reduced to 7 nm, and by 2023 the parameter will reach 5 nm. At the moment, this indicator in the manufactured electronics is 10-14 nm. Improving the dimensions will allow placing on one chip the size of a nail not 30, but 30 billion transistors, thereby doubling the power of any equipment. According to the developer, the 5nm solution is 40% more efficient than the 10nm chips existing on the market, and the power consumption is 75% lower with the same performance. The development is conducted jointly with Samsung and GlobalFoundries. For the past six years, IBM has used the FinFET architecture. In this case, each transistor receives three conductive layers. Now, silicon nanoplates, which are created by the method of UV lithography, will cope with the task. A change in the base is associated with an increase in the number of exits: there will be four of them.